04891753 is referenced by 46 patents and cites 8 patents.

When a load instruction is encountered, a read operation is sent to the bus control logic, the register is marked as busy, and execution proceeds to the next instruction. When an instruction is executed, it proceeds providing that its source and destination registers are not marked busy; otherwise the instruction is retried. When data are returned as the result of a read operation, the destination register(s) are marked as not busy.

Title
Register scorboarding on a microprocessor chip
Application Number
6/935193
Publication Number
4891753
Application Date
November 26, 1986
Publication Date
January 2, 1990
Inventor
Konrad Lai
Aloha
OR, US
Glen Myers
Aloha
OR, US
Michael T Imel
Beaverton
OR, US
Robert Riches
Hillsboro
OR, US
David Budde
Portland
OR, US
Agent
Owen L Lamb
Assignee
Intel Corporation
CA, US
IPC
G06F 9/18
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